✓  Ph.D. Candidate of Electrical and Computer Engineering (Sep 2018- July 2022), University of Saskatchewan, Saskatoon, SK, Canada, Total GPA: 90/100.

✓  Master of Digital Electronics Engineering (2012-2014), Shahid Beheshti University (National University of Iran), Tehran, Iran, Total GPA: 18.75/20 (3.75/4), Ranked the 1st.

✓  B.Sc. in Electronics Engineering (2007–2012), Islamic Azad University, Arak Branch,  Arak, Iran, Total GPA: 16.36/20 (3.272/4), Ranked 4th among 85 people.

✓ Highly capable in ISE and Vivado Foundation and ModelSim

✓ FPGA architecture, design, implementation, synthesis constraints, timing closure, verification, and validation, and place and route with Xilinx FPGA devices

✓ Highly capable in VHDL and Verilog.

✓ Highly capable high-speed memory interface DDR2 and DDR3

✓ Highly capable Standard protocols, such as Ethernet, SPI, I2C, and RS232.

✓ Synopsys design compiler and Cadence SoC Encounter

✓ C++ and Phyton programming and Matlab

✓ Linux

✓ AutoCad, Protel, Labview, Hspice, MS Office, Latex, etc.

✓  Teledyne Technologies, FPGA Design Specialist, Waterloo, Ontario, Canada, Since November 2022.  Designing, Debugging, and implementing on Kintex UltraScale by using Vivado with VHDL. 

✓ University of Saskatchewan, Graduate Researcher, Saskatoon, Saskatchewan, Canada, Sep. 2018 – Jul. 2022. By using ISE and Vivado on Xilinx FPGA with VHDL and C++. Interfacing DDR3 and Ethernet; using RS232, SPI, and I2C protocols. Using Synopsys design compiler and Cadence SoC Encounter and Matlab.

✓ Pishgaman Farda General Trading Company, Electronics Engineer, Arak, Iran, Aug. 2017- Aug 2018. Working with AVR microcontroller by using Code vision with C++ and Matlab,

✓ Microelectronic Lab, Shahid Beheshti University, Part-time Researcher, Tehran, Iran, Nov. 2014- Sep 2016. By using ISE on Xilinx FPGA with VHDL and C++. Using RS232 protocols. Using Synopsys design compiler and Cadence SoC Encounter. Working with AVR microcontroller by using Code vision with C++ and Matlab.

✓Engineering Office 1119 as a trainee for 3 months, Arak, Iran, May 2011 – Aug 2011. By using Autocad Electrical drawing of the building

✓ “An Optimized Hardware Implementation of Modular Multiplication of Binary Ring-LWE”, Microelectronic Lab, University of Saskatchewan, Saskatoon, Canada, Fall 2021. By using Vivado on Xilinx Virtex-7 FPGA with VHDL and C++.

✓ “Design and implementation of a fault resilient Binary Ring-LWE on FPGA,” Microelectronic Lab, University of Saskatchewan, Saskatoon, Canada, Summer 2021. By using VHDL on Xilinx Virtex-7 FPGA.  

✓ “Design and implementation of a post-quantum cryptosystem for resource-constrained devices on ASIC and FPGA,” Microelectronic Lab, University of Saskatchewan, Saskatoon, Canada, Spring and Summer 2020. By using VHDL on Xilinx Spartan-6 and Virtex-7 FPGA and TSMC-65nm by using Synopsys Design Compiler.

✓ “Design and implementation of a nano AES cryptosystem for IoT end-node devices,”. Microelectronic Lab, University of Saskatchewan, Saskatoon, Canada, Fall 2019 and winter 2020. By using VHDL on Xilinx Virtex-5 FPGA and TSMC-65nm by using Synopsys Design Compiler and Cadence SoC Encounter.

✓ “Design and implementation of a high throughput cryptosystem for high traffic application on FPGA,” Microelectronic Lab, University of Saskatchewan, Saskatoon, Canada, Spring and Summer 2019. By using VHDL on Xilinx Virtex-5 FPGA.

✓ “Design and implementation of an architecture for Spiking neural network on FPGA,” Microelectronic Lab, University of Saskatchewan, Saskatoon, Canada, fall 2018 and winter 2019. By using VHDL on Xilinx Virtex-5 FPGA.

✓ “Hardware architecture design for image Steganography algorithms”, Microelectronic Lab, Shahid Beheshti University, Tehran, Iran, fall 2015 – summer 2016. By using VHDL on Xilinx Virtex-5 FPGA.

✓ “Design and implementation of a crypto-system for communication network on FPGA”, Microelectronic Lab, Shahid Beheshti University, Tehran, Iran, fall 2014 – fall 2015. By using VHDL on Xilinx Virtex-5 FPGA.

✓ “Design and simulation of a wide tuning range CMOS voltage controlled oscillator for PLL”, Microelectronic Lab, Shahid Beheshti University, spring 2013. By using Cadence

✓ “Design and simulation of a low power Level Shifter”, Microelectronic Lab, Shahid Beheshti University, spring 2013. By using Cadence

✓ “Design and simulation of a low area Full Adder” Microelectronic Lab, Shahid Beheshti University, summer 2013.

✓ Simulation of SBDN full adder with 1 out of 3 codes, Computer Architecture Lab, fall 2012.

✓ Computer architecture

✓ Hardware Design

✓ Implementation of Cryptography algorithms in FPGAs

✓ Post-Quantum Cryptography and Homomorphic Encryption

✓ Low power and ultra-low power system design

✓ Embedded systems,  VLSI and CMOS Technology

✓ Digital Integrated Circuits design

✓ Arithmetic Circuits

✓ Signal processing

✓ Deep Learning accelerator design

✓ Deep Learning and Machine Learning

Journal 

✓ Karim Shahbazi, and Seok-Bum Ko. "Area and power efficient post-quantum cryptosystem for IoT resource-constrained devices." Microprocessors and Microsystems (2021): 104280. 

✓ Karim Shahbazi and Seok-Bum Ko. "Area-Efficient Nano-AES Implementation for Internet-of-Things Devices." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29.1 (2020): 136-148.

✓ Karim Shahbazi and Seok-Bum Ko. "High throughput and area-efficient FPGA implementation of AES for high-traffic applications." IET Computers & Digital Techniques 14.6 (2020): 344-352.

✓ Wang, Yi, Karim Shahbazi, Hao Zhang, Kwang-Il Oh, Jae-Jin Lee, Seok-Bum Ko. "Efficient spiking neural network training and inference with reduced precision memory and computing." IET Computers & Digital Techniques 13.5 (2019): 397-404.

✓ Karim Shahbazi, Mohammad Eshghi, Reza Faghih Mirzaee., "Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5", Engineering Science and Technology, an International Journal, Elsevier, Volume 20, Issue 4, August 2017.

✓ Karim Shahbazi, Amir Kazemi, Alireza Hassanzadeh, Mohammad Emadi, “Low Power FPGA Implementation of a Transposed Form FIR Filter with Differential Input technique”, International Journal of Computer Applications (0975 – 8887) Volume 142 – No 4, May 2016.

✓ Mehrdad Moradi, Mohammad Eshghi, Karim Shahbazi, “A Trainless Recognition of Handwritten Persian/Arabic Letters using Primitive Elements”, International Journal of Computer Applications (0975 – 8887) Volume 142 – No 11, May 2016. 

✓ Karim Shahbazi, Mohammad Eshghi., "Design of a Specific Instructions Set Processor for AES Algorithm", International Journal of Computer Applications (0975 – 8887) Volume 93 – No 4, May 2014.

✓ Karim Shahbazi, Alireza Hassanzadeh, "A Wide Tuning Range CMOS Voltage Controlled Oscillator", Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 2, May 2014.

Conference

✓  Karim Shahbazi, Seok-Bum Ko “Lightweight and CCA2-Secure Hardware Implementation of Binary Ring-LWE”, ISCAS 2022

✓ Karim Shahbazi., "Risks and vulnerability at SIP", Regional Iranian Conference on Computer Science, 2012, in Persian.

✓ Karim Shahbazi, Somayeh Timarchi, "Simulation of SBDN full adder with 1 out of 3 code",  Second regional Iranian conference on electronics, 2012, in Persian.

✓ Guest Lecture for ‘Deep Learning Architecture’, September 2022, University of Saskatchewan, Saskatoon.

✓ Guest Lecture for ‘Network Architecture and Protocols’, March 2022, University of Saskatchewan, Saskatoon.

✓ Co-speaker for "Post-Quantum IoT Security", CMC Research Workshop – Secure IoT Hardware, 25 February 2022, Online.

✓ Guest Lecture for ‘Deep Learning Architecture’, November 2021, University of Saskatchewan, Saskatoon.

✓ Teacher Assistant in ‘Digital Systems Architecture’, September 2021 to December 2021, University of Saskatchewan, Saskatoon.

✓ Guest Lecture for ‘Network Architecture and Protocols’, February 2021, University of Saskatchewan, Saskatoon.

✓ Teacher Assistant in Microcontrollers, October 2010 to January 2011, Islamic Azad University, Arak branch.

Teaching Training and Certificates

✓ Exam Marking for Engineering, University of Saskatchewan, October 2019

✓ IEEE Transactions on Circuits and Systems II: Express Briefs (Feb 2024) 

✓  International Symposium on Circuits and Systems (ISCAS 2024).

✓ IEEE Transactions on Circuits and Systems II: Express Briefs

✓Security and Communication Networks, hindawi 

✓ International Symposium on Circuits and Systems (ISCAS 2022).

✓ IEEE Internet of Things Journal.

✓ IEEE Access.

✓ Journal of Circuits, Systems, and Computers (JCSC).

✓ Journal of Advances in Computer Engineering and Technology.

✓ The poster judges at 1st Engineering Graduates Research (EGR) Conference, University of Saskatchewan, (Sep 2019).

✓ Electrical and Electronics Engineering: An International Journal (ELELIJ).

✓ International Journal of Computer and Information Technology (IJCIT).

✓ Journal of Applied Research in Electrical Engineering (JAREE)